/************************************************************************
  * Copyright(c) 2023 Levetop Semiconductor Co.,Led. All rights reserved.
  * @file     dma.c
  * @author   UartTFT Application Team
  * @version  V0.0.1
  * @date     2023-01-01
  * @brief    
 *************************************************************************/

#include "dma.h"
#include "spi_drv.h"

/* global struct variable for for Channel registers*/
/* global struct variable for for DMAC registers*/
//--spi screen
DMA_CHANNEL_REG *TFTspi_dma_channel[DMAC_CHNUM] = {(DMA_CHANNEL_REG *)(TFTSPI_DMA_BASE_ADDR), (DMA_CHANNEL_REG *)(TFTSPI_DMA_BASE_ADDR + 0x58),
												   (DMA_CHANNEL_REG *)(TFTSPI_DMA_BASE_ADDR + 0xB0), (DMA_CHANNEL_REG *)(TFTSPI_DMA_BASE_ADDR + 0x108)};
DMA_CONTROL_REG *TFTspi_dma_control = (DMA_CONTROL_REG *)(TFTSPI_DMA_BASE_ADDR + 0x2C0);

//--SD_SPI_dma
DMA_CHANNEL_REG *SDSPI_dma_channel[DMAC_CHNUM] = {(DMA_CHANNEL_REG *)(SDSPI_DMA_BASE_ADDR), (DMA_CHANNEL_REG *)(SDSPI_DMA_BASE_ADDR + 0x58),
												  (DMA_CHANNEL_REG *)(SDSPI_DMA_BASE_ADDR + 0xB0), (DMA_CHANNEL_REG *)(SDSPI_DMA_BASE_ADDR + 0x108)};
DMA_CONTROL_REG *SDSPI_dma_control = (DMA_CONTROL_REG *)(SDSPI_DMA_BASE_ADDR + 0x2C0);

//--exflash
DMA_CHANNEL_REG *exFlash_dma_channel[DMAC_CHNUM] = {(DMA_CHANNEL_REG *)(exFlash_DMA_BASE_ADDR), (DMA_CHANNEL_REG *)(exFlash_DMA_BASE_ADDR + 0x58),
													(DMA_CHANNEL_REG *)(exFlash_DMA_BASE_ADDR + 0xB0), (DMA_CHANNEL_REG *)(exFlash_DMA_BASE_ADDR + 0x108)};
DMA_CONTROL_REG *exFlash_dma_control = (DMA_CONTROL_REG *)(exFlash_DMA_BASE_ADDR + 0x2C0);

//--COMuart
DMA_CHANNEL_REG *COMuart_dma_channel[DMAC_CHNUM] = {(DMA_CHANNEL_REG *)(COMuart_DMA_BASE_ADDR), (DMA_CHANNEL_REG *)(COMuart_DMA_BASE_ADDR + 0x58),
													(DMA_CHANNEL_REG *)(COMuart_DMA_BASE_ADDR + 0xB0), (DMA_CHANNEL_REG *)(COMuart_DMA_BASE_ADDR + 0x108)};
DMA_CONTROL_REG *COMuart_dma_control = (DMA_CONTROL_REG *)(COMuart_DMA_BASE_ADDR + 0x2C0);

//--WAVdac
DMA_CHANNEL_REG *WAVdac_dma_channel[DMAC_CHNUM] = {(DMA_CHANNEL_REG *)(WAVdac_DMA_BASE_ADDR), (DMA_CHANNEL_REG *)(WAVdac_DMA_BASE_ADDR + 0x58),
												   (DMA_CHANNEL_REG *)(WAVdac_DMA_BASE_ADDR + 0xB0), (DMA_CHANNEL_REG *)(WAVdac_DMA_BASE_ADDR + 0x108)};
DMA_CONTROL_REG *WAVdac_dma_control = (DMA_CONTROL_REG *)(WAVdac_DMA_BASE_ADDR + 0x2C0);

												   
												   
												   
void SPI2_DMA_Tran(uint8_t *Tx_Addr, uint8_t *Rx_Addr, uint32_t length)
{
	DMA_Init(DMA1_BASE_ADDR);
	SPI2->SPIDMACR |= 0x03; // enable SPI TX RX DMA

	m_dma_control->DMA_CONFIG = 1;
	// tx
	m_dma_channel[0]->DMA_SADDR = (uint32_t)Tx_Addr;
	m_dma_channel[0]->DMA_DADDR = (uint32_t)&SPI2->SPIDR;
	m_dma_channel[0]->DMA_CTRL_HIGH = length;
	m_dma_channel[0]->DMA_CTRL = DNOCHG | SIEC | M2P_DMA;
	m_dma_channel[0]->DMA_CFG = (HS_SEL_SRC_SOFT);
	m_dma_channel[0]->DMA_CFG_HIGH = DST_PER_SPI_TX(1) | SRC_PER_SPI_TX(1);

	// rx
	m_dma_channel[1]->DMA_SADDR = (uint32_t)&SPI2->SPIDR;
	m_dma_channel[1]->DMA_DADDR = (uint32_t)Rx_Addr;
	m_dma_channel[1]->DMA_CTRL_HIGH = length;
	m_dma_channel[1]->DMA_CTRL = SNOCHG | DIEC | P2M_DMA;
	m_dma_channel[1]->DMA_CFG = (HS_SEL_DST_SOFT);
	m_dma_channel[1]->DMA_CFG_HIGH = SRC_PER_SPI_RX(4) | DST_PER_SPI_RX(4);

	m_dma_control->DMA_MASKTFR = CHANNEL_UMASK(0) | CHANNEL_UMASK(1);
	m_dma_control->DMA_CHEN = CHANNEL_WRITE_ENABLE(0) | CHANNEL_ENABLE(0) | CHANNEL_WRITE_ENABLE(1) | CHANNEL_ENABLE(1);
}

void SPI2_DMA_Wait(void)
{
	while ((m_dma_control->DMA_RAWTFR & (CHANNEL_STAT(0) | CHANNEL_STAT(1))) != (CHANNEL_STAT(0) | CHANNEL_STAT(1)))
		;

	m_dma_control->DMA_CLRTFR = (CHANNEL_STAT(0) | CHANNEL_STAT(1));

	m_dma_control->DMA_CHEN = 0;
	m_dma_control->DMA_CONFIG = 0;
	SPI2->SPIDMACR &= ~0x03; // diable SPI TX RX DMA
}
